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1
E00Z52
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any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
ICX279AL
14 pin DIP (Plastic)
Description
The ICX279AL is an interline CCD solid-state
image sensor suitable for CCIR B/W video cameras
with a diagonal 4.5mm (Type 1/4) system. Compared
with the current product ICX209AL, basic
characteristics such as sensitivity, smear and
dynamic range are improved drastically from visible
light region to near infrared light region through the
adoption of EXview HAD CCD
TM
technology.
This chip features a field period readout system and
an electronic shutter with variable charge-storage time.
The package is a 10mm-square 14-pin DIP (Plastic).
Features
Sensitivity in near infrared light region
(+5dB compared with the ICX209AL,
= 945nm)
High sensitivity (+6dB compared with the ICX209AL, no IR cut filter)
Low smear (20dB compared with the ICX209AL)
High D range (+2dB compared with the ICX209AL)
Horizontal register: 3.3 to 5V drive
Reset gate:
3.3 to 5V drive
No voltage adjustment
(Reset gate and substrate bias are not adjusted.)
High resolution and low smear
Excellent antiblooming characteristics
Continuous variable-speed shutter
Recommended range of exit pupil distance: 20 to 100mm
Device Structure
Interline CCD image sensor
Image size:
Diagonal 4.5mm (Type 1/4)
Number of effective pixels: 752 (H)
582 (V) approx. 440K pixels
Total number of pixels:
795 (H)
596 (V) approx. 470K pixels
Chip size:
4.43mm (H)
3.69mm (V)
Unit cell size:
4.85m (H)
4.65m (V)
Optical black:
Horizontal (H) direction : Front 3 pixels, rear 40 pixels
Vertical (V) direction
: Front 12 pixels, rear 2 pixels
Number of dummy bits:
Horizontal 22
Vertical 1 (even fields only)
Substrate material:
Silicon
Optical black position
(Top View)
2
12
V
H
Pin 1
Pin 8
40
3
EXview HAD CCD is a trademark of Sony Corporation.
EXview HAD CCD is a CCD that drastically improves light efficiency by including near infrared light region as a basic structure of
HAD (Hole-Accumulation-Diode) sensor.
TM
Diagonal 4.5mm (Type 1/4) CCD Image Sensor for CCIR B/W Video Cameras
2
ICX279AL
Block Diagram and Pin Configuration
(Top View)
Note)
Note) : Photo sensor
V
OUT
GND
V
1
V
2
V
3
V
4
V
DD
GND
SUB
V
L
RG
H
1
H
2
Horizontal Register
V
e
r
tical Register
NC
7
6
5
4
3
2
1
8
9
10
11
12
13
14
Pin Description
Absolute Maximum Ratings
1
+24V (Max.) when clock width < 10s, clock duty factor < 0.1%.
Pin No. Symbol
Description
Pin No.
Symbol
Description
1
2
3
4
5
6
7
V
4
V
3
V
2
V
1
NC
GND
V
OUT
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
GND
Signal output
8
9
10
11
12
13
14
V
DD
GND
SUB
V
L
RG
H
1
H
2
Supply voltage
GND
Substrate clock
Protective transistor bias
Reset gate clock
Horizontal register transfer clock
Horizontal register transfer clock
Item
V
DD
, V
OUT
, RG
SUB
V
1
, V
3
SUB
V
2
, V
4
, V
L
SUB
H
1
, H
2
, GND
SUB
V
DD
, V
OUT
, RG GND
V
1
, V
2
, V
3
, V
4
GND
H
1
, H
2
GND
V
1
, V
3
V
L
V
2
, V
4
, H
1
, H
2
, GND V
L
Voltage difference between vertical clock input pins
H
1
H
2
H
1
, H
2
V
4
Against
SUB
Against GND
Against V
L
Between input clock
pins
Storage temperature
Operating temperature
40 to +8
50 to +15
50 to +0.3
40 to +0.3
0.3 to +18
10 to +18
10 to +6
0.3 to +28
0.3 to +15
to +15
5 to +5
13 to +13
30 to +80
10 to +60
V
V
V
V
V
V
V
V
V
V
V
V
C
C
1
Ratings
Unit
Remarks
3
ICX279AL
Clock Voltage Conditions
Bias Conditions
1
V
L
setting is the V
VL
voltage of the vertical transfer clock waveform, or the same power supply as the V
L
power supply for the V driver should be used.
2
Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated
within the CCD.
DC Characteristics
Supply current
Item
I
DD
Symbol
4
Min.
Unit
Remarks
Typ.
Max.
mA
6
Readout clock voltage
Vertical transfer clock
voltage
Horizontal transfer
clock voltage
Reset gate clock
voltage
Substrate clock voltage
Item
V
VT
V
VH1
, V
VH2
V
VH3
, V
VH4
V
VL1
, V
VL2
,
V
VL3
, V
VL4
V
V
V
VH3
V
VH
V
VH4
V
VH
V
VHH
V
VHL
V
VLH
V
VLL
V
H
V
HL
V
RG
V
RGLH
V
RGLL
V
RGL
V
RGLm
V
SUB
Symbol
14.55
0.05
0.2
8.0
6.3
0.25
0.25
3.0
0.05
3.0
21.0
Min.
15.0
0
0
7.0
7.0
3.3
0
3.3
22.0
Typ.
15.45
0.05
0.05
6.5
8.05
0.1
0.1
0.3
0.3
0.3
0.3
5.25
0.05
5.5
0.4
0.5
23.5
Max.
Unit
1
2
2
2
2
2
2
2
2
2
2
3
3
4
4
4
5
Waveform
diagram
V
VH
= (V
VH1
+ V
VH2
)/2
V
VL
= (V
VL3
+ V
VL4
)/2
V
V
= V
VH
n V
VL
n (n = 1 to 4)
High-level coupling
High-level coupling
Low-level coupling
Low-level coupling
Input through 0.1F
capacitance
Low-level coupling
Low-level coupling
Remarks
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Supply voltage
Protective transistor bias
Substrate clock
Reset gate clock
Item
V
DD
V
L
SUB
RG
Symbol
15.0
1
2
2
Min.
V
Unit
Remarks
Typ.
Max.
14.55
15.45
4
ICX279AL
Horizontal transfer clock equivalent circuit
Vertical transfer clock equivalent circuit
Reset gate clock equivalent circuit
H
1
H
2
C
H1
C
H2
C
HH
R
H
R
H
V
1
C
V12
V
2
V
4
V
3
C
V34
C
V23
C
V41
C
V13
C
V24
C
V1
C
V2
C
V4
C
V3
R
GND
R
4
R
1
R
3
R
2
R
RG
RG
C
RG
Clock Equivalent Circuit Constant
C
V1
, C
V3
C
V2
, C
V4
C
V12
, C
V34
C
V23
, C
V41
C
V13
C
V24
C
H1
, C
H2
C
HH
C
RG
C
SUB
R
1
, R
2
, R
3
, R
4
R
GND
R
H
R
RG
Symbol
Capacitance between vertical transfer clock
and GND
Capacitance between vertical transfer clocks
Capacitance between horizontal transfer clock
and GND
Capacitance between horizontal transfer clocks
Capacitance between reset gate clock and GND
Capacitance between substrate clock and GND
Vertical transfer clock series resistor
Vertical transfer clock ground resistor
Horizontal transfer clock series resistor
Reset gate clock series resistor
Item
Min.
1200
680
220
150
82
75
22
36
5
180
82
15
12
51
Typ.
Max.
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
Unit Remarks
5
ICX279AL
Drive Clock Waveform Conditions
(1) Readout clock waveform
(2) Vertical transfer clock waveform
V
VH
= (V
VH1
+ V
VH2
)/2
V
VL
= (V
VL3
+ V
VL4
)/2
V
V
= V
VH
n V
VL
n (n = 1 to 4)
100%
90%
10%
0%
tr
tf
0V
twh
M
2
M
V
VT
V
VH1
V
VHH
V
VHL
V
VH
V
VLH
V
VL1
V
VLL
V
VHL
V
VHH
V
VL
V
VHH
V
VH
V
VLH
V
VLL
V
VL
V
VHL
V
VL3
V
VHL
V
VH3
V
VHH
V
VH2
V
VHH
V
VHH
V
VHL
V
VHL
V
VH
V
VLH
V
VL2
V
VLL
V
VL
V
VH
V
VL
V
VHL
V
VLH
V
VLL
V
VHL
V
VH4
V
VHH
V
VHH
V
VL4
V
1
V
3
V
2
V
4
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